High-Level Synthesis for Nanoscale Integrated Circuits

OF THE DISSERTATION High-Level Synthesis for Nanoscale Integrated Circuits by Bin Liu Doctor of Philosophy in Computer Science University of California, Los Angeles, 2012 Professor Jason Cong, Chair Increased design complexity and time-to-market pressure in the integrated circuit (IC) industry call for a raised level of abstraction at which designs are specified. High-level synthesis is the process of generating register-transfer level (RTL) implementations from behavioral specifications, and it is the key enabler for a designing at a higher level beyond RTL. As IC manufacturing technology scales down to nanoscopic scale, the synthesis tools face a number of new challenges, including complexity, power and interconnect. In this dissertation, we propose a spectrum of new techniques in highlevel synthesis to address the new challenges and to improve the quality of synthesis results. 1. Efficient and versatile scheduling engine using soft constraints. We present a scheduler that distinguishes soft constraints from hard constraints when exploring the design space, and identify a class of tractable scheduling problems with soft constraints. By exploiting the total unimodularity of the constraint matrix in an integer-linear programming formulation, we are able to solve the problem optimally in polynomial time. Compared to traditional methods, the proposed approach allows easier expression of various design intentions and optimization directions, and, at the same time, gives the scheduler freedom to make global trade-offs optimally. We show that this scheduling engine is flexible